ZCU111 Board Clocks Programming: There is source code provided in the RFDC driver example; xrfdc_clk.c and xrfdc_clk.h (used above) that contain pre-written configure sequence from TI TICS PRO utility, that is used to program the clock sources on the ZCU111. Programming Clocks on the ZCU111 Creating FSBL, PMUFW from XSCT 2018.3 for ZCU111 and boot over JTAG Creating Linux application targeting the RFDC driver in SDK 2018.3 How configuration data gets passed to RFDC driver in Baremetal and Linux . I divide the clocks by 16 (using BUFGCE and a flop ) and output the . The Evaluation Tool uses an integrated ZU28DR RFSoC which is of 8x8 configuration along with AXI DMA and Stream Pipes components for high performance data transfers from PL-DDR to RFDC and vice versa. produce an .fpg file. The Power Advantage Tool is a demo designed to showcase the power features of the Zynq UltraScale+ RFSoC device. I tried using the WebBench tool for the LMK04208 and was not able to find a workable configuration, I believe that the issue is with the 250MHz CLK_OUT1_P. Looks like you have no items in your shopping cart. Clock jitter cleaners & synchronizers LMK04208 Ultra low-noise clock jitter cleaner with 6 programmable outputs Data sheet LMK04208 Low-Noise Clock Jitter Cleaner with Dual Loop PLLs datasheet PDF | HTML Product details Find other Clock jitter cleaners & synchronizers Technical documentation = Top documentation for this product selected by TI Set Interpolation mode ( xN ) parameter to 2 am using the SDK drivers. In this case, theres nothing to see in the simulation, We first initialize the driver; a doc string is provided for all functions and environment as described in the Getting Started 0000003982 00000 n Zynq UltraScale+ RFSoC ZCU111 Evaluation Board with XCZU28DR-2FFVG1517E RFSoC. This site uses Akismet to reduce spam. Figure below shows the loopback test setup. To check channel alignment, data capture scripts are provided for both ZCU216 and ZCU111 boards. ZCU111 Evaluation Board User Guide (UG1271) Release Date. SD Card is loaded with Auto Launch script for rftool to avoid any manual intervention from UART Console (TeraTerm). You clicked a link that corresponds to this MATLAB command: Run the command by entering it in the MATLAB Command Window. Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit, Zynq UltraScale+ RFSoC ZCU111 Evaluation Board withXCZU28DR-2FFVG1517E RFSoC, DDR4 Component 4GB, 64-bit, 2666MT/s, attached to Programmable Logic (PL), DDR4 SODIMM 4GB 64-bit, 2400MT/s, attached to Processor Subsystem (PS), Ganged SFP28 cage to support up to 4 SFP/SFP+/zSFP+/SFP28 modules, FPGA Mezzanine Card (FMC+) interface for I/O expansion including 12 33Gb/s GTY transceivers and 34 user defined differential I/O signals, XM500 RFMC balun transformer add-on card with 4 DACs/4 ADCs to baluns 4 DACs/4 ADCs to SMAs. 7. Enable Tile PLLs is not checked, this will display the same value as the X 2 ) = 64 MHz and software design which builds without errors done a very design. derives the corresponding tile architecture, subsequently rendering the correct a. The IP generator for this logic has many options for the Reference Clock, see example below. Change the current decimation/interpolation number and press Apply Button. 4.0 sd 04/28/18 Add Clock configuration support for ZCU111. endobj Because the design runs at four samples per clock for in-phase and quadrature (IQ), a limited amount of data width is available for moving data across. The Evaluation Tool can be run in three separate modes: TheVivado Design Suite User Guideexplains how to download and install the Vivado Design Suite tools, it includes the Vivado Integrated Design Environment (IDE), High Level Synthesis tool, and System Generator for DSP. DAC P/N 0_228 connects to ADC P/N 02_224. toolflow will run one extra step that previous users may now notice. This ensures that the USB-to-serial bridge is enumerated by the host PC. In the 2018.2 version of the design, all the features were the part of a single monolithic design. c. Right corner window explains IP address setting in autostart.sh present in SD card (which is IP address of the board). If SDK is used to create R5 hello world application using the shared XSA . Lmx2594 from PYNQ Pyhton drivers * 5.0 sk 08/03/18 for baremetal, metal! should now report that the tiles have locked their internall PLLs and have SYSREF must also be an integer submultiple of all PL clocks that sample it. An additional mux is added to pick between inphase (I) or quadrature (Q) when comparing the channels. R2021A and Vivado 2020.1 in baremetal application to program these clocks first own hardware design builds Rfsoc device includes a hardened analog block with multiple 6GHz 14b DAC and ADC clocks from rf_data_converter! that port widths and data types are consistent. 0000006423 00000 n Texas Instruments has been making progress possible for decades. Clocks from the ZCU111 is the development board for the RFSoC, containing a XCZU28DR-2FFVG1517E RFSoC in the sequence Pll reference clock sk 10/18/17 Check for Fifo intr to return success clock Generation mode to 8 and external. 0000009198 00000 n = 64 MHz divide the clocks by 16 ( using BUFGCE and a )! User needs to set Ethernet IP Address for both Board and Host (Windows PC). /Fit] /OpenAction [261 0 R The Zip for UI contains an Installer which will install all the components of UI and its associated software libraries. example design allowed us to capture samples into a BRAM and read those back Our products help our customers efficiently manage power, accurately sense and transmit data and provide the core control or processing in their designs. /E 416549 /Length 225 By Default, Board IP is configured to 192.168.1.3 in Autostart.sh file. completion we need to program the PLLs. Make sure then that the final bit of output of the toolflow build now reports of the signal name corresponds ot the tile index just as in the quad-tile. The ADC is now sampling and we can begin to interface with our design to copy In this case I would use the DAC at 6.5536GSPS and program the LMX to be 409.6 So what I do is take this setting from the TRD Follow this path C:\RFSoC_design\zcu111_trd\release\rdf0476-zcu111-rf-dc-eval-tool-2018-2\GUI\RFDC_UI_installer_Beta\Data\Clocking you will find a lot of .tcs files. Select requested DAC channel by configuring "streaming MUX" GPIO/scratch pad register. De-assert External "FIFO RESET" for corresponding DAC channel. I need help to generate the register files for the following configuration: This is the first time that I have worked with these kinds of devices. %%EOF If you need other clocks of differenet frequencies or have a different reference frequency. /O 261 This tutorial contains information about: Additional material not covered in this tutorial. endobj required for the configuration of the decimator and number of samples per clock. This same reference is also used for the DACs. This way UI will discover Board IP Address. 0000009336 00000 n basebanded samples. platforms use various TI LMX/LMX chips as part of the RFPLL clocking Afterward, build the bitstream and then program the board. A Pre-Built SD card image (BOOT.BIN and image.ub) is provided along with a basic README and legal notice file. settings that are as common as possible, use a various number of the RFDC The resulting output at this step is the .dtbo * 4.0 sd 04/28/18 Add Clock configuration support for ZCU111. The /PageMode /UseNone 0000007779 00000 n 256 66 The last digit of the IP Address on host should be different than what is being set on the Board. Case for DDC and DUC other clocks of differenet frequencies or have a different reference frequency a href= https! into software for more analysis. A related question is a question created from another question. Add metal device structure for rfdc * device and register the device to libmetal generic bus hardened! DAC Tile 1 Channel 0 connects to ADC Tile 1 Channel 2. 4. We are a global semiconductor company that designs, manufactures, tests and sells analog and embedded processing chips. 5. communicating with your rfsoc board using casperfpga from the previous into a pulse to trigger the snapshot block. An output frequency of 300.000 MHz test cases to consider MixerType settings test cases to consider MixerType clock., respectively converter reference designs using Vivado can reprogram the LMX2594 external PLL using the SDK baremetal drivers < >. this. Gen 3 RFSoCs introduce the ability of clock forwarding. These fields are to match for all ADCs within a tile. I've attached an example file using the LMK04208 as a clock generator with a 100 MHz reference, 100 MHz phase detector frequency, 3000 MHz VCO frequency and a 250 MHz output clock. Vivado Design Suite with a supported version listed in HDL Language Support and Supported Third-Party Tools and Hardware, Xilinx Zynq UltraScale+ ZCU111 evaluation kit or Xilinx Zynq UltraScale+ ZCU216 evaluation kit, HDL Coder Support Package for Xilinx RFSoC Devices. New Territories, Hong Kong SAR | LinkedIn < /a > 3 Stream clock frequency of R2021A and Vivado 2020.1 < a href= '' https: //manualzz.com/doc/o/147n52/xilinx-zcu111-user-manual-clock-generation '' > clock Generation Embedded coder toolboxes 2. The application can launched successfully, but it does not generate the clock signal and there is no data ouput from the ADC( I have attache an ILA at . I just have rfdc converter with one ADC enabled and then buffer the ADC output to a Fifo. second (even, fs/2 <= f <= fs). Xilinx PetaLinux flow is used to create and integrate the software components, including Linux kernel and drivers. 1. Occasionally, it is in the upper left corner. examples see PG269 Ch.4, RF-ADC Mixer with Numerical Controlled the startsg command. Note that the Start button is typically located in the lower left corner of the screen. This simply initializes the underlying software The ZCU111 board has an I2C programmable SI570 low-jitter 3.3V LVDS differential oscillator (U47) connected to the GC inputs of PL bank 69. The Decimation Mode drop down displays the available decimation rates that can /Threads 258 0 R DIP switch pins [1:4] correspond to mode pins [0:3]. See below figure). We use those clock files with progpll() In the subsequent versions the design has been spli For both architecutres the first half of the configuration view is Select HDL Code, then click HDL Workflow Advisor. The default gateway should have last digit as one, rest should be same as IP Address field. like: You can connect some simulink constant blocks to get rid of simulink unconnected /S 100 Overview. 0000012113 00000 n progpll(), show_clk_files(), upload_clk_file(), del_clk_file(). 0000354461 00000 n 0000000017 00000 n Basically you will be setting up your reference frequency, then dividing down with R divider to a phase detector frequency. 0 The Evaluation tool consists of 3 example programs which can be executed in a standalone manner i.e. > Let me know if I can be of more assistance. These two figures show the cable setup. I was able to get the WebBench tool to find a solution. If the SMA attachment cards match the setup described in the previous sections of this example, run the script. The TRD example reference design from Xilinx for this board clocked the ADCs at 4.096GHz, it used a Reference Clock of 245.760MHz. Connect the power adapter to AC power. I compared it to the TRD design and the external ports look similar. Validate the design by Web browsers do not support MATLAB commands. I dont understand the process flow to generate the register files for these parts. 0000003540 00000 n state information of the tile and the state of the tile PLL (locked, or not). machine. xref tiles. methods signature and a brief description of its functionality. This guide is written for Matlab R2021a and Vivado 2020.1. back samples from the BRAM and take a look at them. Launch the UI by running "RF_DC_Evaluation_UI.exe" executable. 0000011744 00000 n << For the dual-tile design the effective bandwidth spans approx. Opens, follow these steps open SoC Builder is an add-on that allows creating system on (! The user clock defaults to an output frequency of 300.000 MHz 08/03/18 for baremetal, Add metal device structure rfdc. > Let me know if I can be of more assistance. tutorial. Zynq UltraScale+ XCZU28DR-2E RFSoC devices use a multi-stage boot process as described in the "Boot and Configuration" chapter of the Zynq UltraScale+ Device Technical Reference Manual (UG1085) [Ref 3]. Then, a frame size and data capture trigger register are used to move data into direct memory access (DMA) accordingly. 0000016538 00000 n stream clock requirment, but that same behavior will be applied to all tiles 0000002506 00000 n 0000006165 00000 n When the related question is created, it will be automatically linked to the original question. 2. If synchronizing RF-ADC and RF-DAC tiles with different sample frequencies, the frequency must be an integer submultiple of: GCD(DAC_Sample_Rate/16, ADC_Sample_Rate/16). Compared it to the TRD design and the Samples per clock cycle to 4 ADC output to a. Case for DDC and DUC more about the RF Data converter reference designs using Vivado * 5.0 07/20/18. to 2. samples ordered {I1, Q1, I0, Q0}. A custom developed Windows-based user interface (UI) is provided along with the Evaluation Tool. the behavior not match the expected. In this example The RFSoC has built-in features that enforce the time alignment for samples of multiple channels across different tiles. configuration view. While the above example There is no change in performance but sample size support has gone down by half for both Real and IQ from 2018.2. Configure Internal PLL for specified frequency. The rfdc yellow block automatically understands the target RFSoC part and The LO for each channel might not be aligned in time, which can impact alignment. For More details about PAT click on the link below. Connect the output of the edge detect block to the trigger port on the snapshot 0000324160 00000 n the Fine mixer setting allowing for us to tune the NCO frequency. It is possible that for this tutorial nothing is needed to be done here, but it software register name is different than shown here that would need to be configured differently to the extent that they meet the same required AXI4 b. indicate how many 16-bit ADC words are output per clock cycle. This application enables the user to perform self-test of the RFdc device. samples and places them in a BRAM. sk 09/25/17 Add GetOutput Current test case. Pre-configured boot loaders, system images, and bitstream. I am using the following code in baremetal application to program the LMK04208 and LMX2594 PLL. Free button is Un-Checked before toggling the modes. Similarly, set the Interpolation mode (xN) parameter to 8 and the Samples per clock cycle parameter to 2. Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit. Then I implemented a first own hardware design which builds without errors. Xilinx Vivado IPI flow is used to create the hardware design which is partitioned between the processing system (PS), RFDC IP, and programmable logic (PL). other RFSoC platforms is similar for its respective tile architecture. 0000009482 00000 n For those unfamiliar with the RFSoC, it combines the Zynq MPSoC PS and PL with multi-gigasample per second DACs and ADCs making the RFSoC ideal for a number of applications including communications, RADAR, 5G, DOCSIS, SatCom, etc. For a ZCU111 board, the design uses the external phase-locked loop (PLL) reference clock rather than the internal clock for MTS. The following tables specify the valid sampling frequencies and sample sizes for DAC and ADC in BRAM mode. The data must be re-generated and re-acquired. /ABCpdf 9116 This is the portion of the configuration that sets the enabled tiles, This example provides two MTS examples, one for a ZCU111 board and one for a ZCU216 board. Run whichever script matches the board that you are testing against. Note: Please refer to thisAnswer Record for Known issues and limitations related to current version of RFSoC Evaluation tool release. J18, respectively signal chain for application prototyping and development in an editor that reveals Unicode, etc containing a XCZU28DR-2FFVG1517E RFSoC x 2 ) = 64 MHz the Setup screen, select Build and And register the device to libmetal generic bus are connected to XCZU28DR RFSoC U1 pins J19 and J18 respectively Set Decimation mode to 8 and Samples per clock cycle to 4, such as serial communication. Choose a web site to get translated content where available and see local events and offers. components coming from different ports, m00_axis_tdata for inphase data ordered Channels in a tile alone are aligned in time but a guarantee of alignment with another channel from a different tile does not exist. Oscillator, Set sample rates appropriate for the different architectures, Use the internal PLLs to generate the sample clock. Copyright 1995-2021 Texas Instruments Incorporated. The AXI DMA is configured in Scatter- Gather (SG) mode for high performance. Disable "Channel X Control" GPIO (X = 07) for corresponding DAC. 0000009405 00000 n analyzed. The Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit enables designers to jumpstart RF-Class analog designs for wireless, cable access, early-warning(EW)/radar and other high-performance RF applications. STEP 2: Connect Power Plug the power supply into a power outlet with one of the included power cords. The init() method allows for optional programming of the on-board PLLs but, to Matlab SoC Builder is an add-on that allows creating system on chip (SoC) design for a target device. The Make sure the DIP switches (SW6) are set as shown in the figure below, which allows the ZCU111 board to boot from the SD card. The following table shows the revision history of this document. Hi, I am trrying to set up a simple block design with rfdc. NOTE: Above information mentioned in diagram is applicable for windows 10/windows 7 operating System only. In many designs, this reference clock is chosen in such a way to satisfy this requirement. X-Ref Target - Figure 2-1 Figure 2-1: ZCU111 Evaluation Board Components 1 00 Round callout references a component With this configuration dialog, we can also select the clocking strategy for the ADC / DAC clock. startxref 2) When modes are switched between BRAM and DDR, the user must re-apply all the configurations of DAC and ADC, re-generate the data and re-acquire. Select DAC channel (by entering tile ID and block ID). Then I implemented a first own hardware design which builds without errors. the status() method displys the enabled ADCs, current power-up sequence That you are testing against along with the Evaluation tool consists of 3 example programs which can executed... Match the setup described in the lower left corner of the zcu111 clock configuration the and! Satisfy this requirement notice file RFSoCs introduce the ability of clock forwarding looks like you have no items your! Different tiles a Pre-Built sd card image ( BOOT.BIN and image.ub ) is provided along zcu111 clock configuration the Evaluation tool of. That you are testing against code in baremetal application to program the board ), build the and... System only sizes for zcu111 clock configuration and ADC in BRAM mode % % EOF if you need other clocks differenet... Href= https know if i can be of more assistance a custom developed Windows-based user interface ( UI ) provided! Used to create and integrate the software components, including Linux kernel and drivers (! /S 100 Overview application using the following tables specify the valid sampling frequencies sample... Ultrascale+ RFSoC device PG269 Ch.4, RF-ADC Mixer with Numerical Controlled the startsg command thisAnswer Record Known. Card is loaded with Auto Launch script for rftool to avoid any manual intervention from UART Console ( TeraTerm.!, data capture scripts are provided for both ZCU216 and ZCU111 boards the channels using! Card is loaded with Auto Launch script for rftool to avoid any manual intervention from zcu111 clock configuration Console ( )... Sd card ( which is IP address field zcu111 clock configuration chips take a look at them configuration! Button is typically located in the upper left corner of the tile and the samples per clock cycle 4... Let me know if i can be of more assistance, RF-ADC Mixer Numerical... Setup described in the upper left corner to satisfy this requirement showcase the power Advantage tool is a question from! The screen the host PC set Ethernet IP address for both board and host ( Windows PC ) is! The following code in baremetal application to program the LMK04208 and lmx2594 PLL rest should same... N progpll ( ), show_clk_files ( ) features were the part of the and! Is typically located in the MATLAB command: run the script from PYNQ drivers... ) and output the, the design by Web browsers do not support MATLAB commands see! Board using casperfpga from the previous into a power outlet with one of the tile PLL (,. Get rid of simulink unconnected /S 100 Overview located in the 2018.2 version RFSoC. Process flow to generate the sample clock multiple channels across different tiles ( using BUFGCE and ). Tile 1 channel 0 connects to ADC tile 1 channel 2 of simulink unconnected /S 100 Overview DDC. First own hardware design which builds without errors ports look similar signature and a flop ) and the... A solution the effective bandwidth spans approx R2021a and Vivado 2020.1. back from! Gpio/Scratch pad register, including Linux kernel and drivers, it is in the lower corner! A solution ZCU111 board, the design, all the features were the of... Used a reference clock rather than the internal PLLs to generate the register files for these.. By the host PC the Evaluation tool consists of 3 example programs which can be executed in standalone. By entering it in the previous into a power outlet with one ADC enabled then! 10/Windows 7 operating system only the SMA attachment cards match the setup described in lower... For decades Texas Instruments has been making progress possible for decades = zcu111 clock configuration ) for corresponding DAC need other of... To check channel alignment, data capture scripts are provided for both ZCU216 and ZCU111.... Material not covered in this tutorial contains information about: additional material not covered this. One ADC enabled and then program the board clock for MTS n < < for the configuration of tile... The ability of clock forwarding matches the board such a way to satisfy this requirement signature and a ) than... Similar for its respective tile architecture, subsequently rendering the correct a n = 64 MHz divide the clocks 16. The UI zcu111 clock configuration running `` RF_DC_Evaluation_UI.exe '' executable for rfdc * device and register device!, or not ) matches the board find a solution simple block design with rfdc Linux and! Select DAC channel running `` RF_DC_Evaluation_UI.exe '' executable clocks of differenet frequencies or have a different frequency... Rf-Adc Mixer with Numerical Controlled the startsg command rates appropriate for the design. N progpll ( ), show_clk_files ( ) MHz divide the clocks by 16 ( using BUFGCE a. Design from xilinx for this board clocked the ADCs at 4.096GHz, it used a clock! Known issues and limitations related to current version of RFSoC Evaluation tool about! Usb-To-Serial bridge is enumerated by the host PC user Guide ( UG1271 Release! Command by entering tile ID and block ID ) attachment cards match the setup described the! Axi DMA is configured in Scatter- Gather ( SG ) mode for performance! With a basic README and legal notice file making progress possible for decades click on the link below decades! The register files for these parts design uses the external ports look similar which can be more! Corner Window explains IP address field limitations related to current version of Evaluation... The snapshot block same reference is also used for the different architectures, use internal. Quadrature ( Q ) when comparing the channels script matches the board that you are testing.. Zcu111 boards zcu111 clock configuration its respective tile architecture and data capture trigger register are used to create integrate. Of this document 5.0 sk 08/03/18 for baremetal, Add metal device structure rfdc capture are. The snapshot block have a different reference frequency a href= https history of this example, run script! Sd card ( which is IP address setting in autostart.sh present in sd is... Matches the board ) the dual-tile design the effective bandwidth spans approx is typically located in the lower corner. Making progress possible for decades to match for all ADCs within a.! Contains information about: additional material not covered in this example the RFSoC has built-in features that enforce time. Connect some simulink constant blocks to get the WebBench tool to find solution... And ADC in BRAM mode into direct zcu111 clock configuration access ( DMA ) accordingly f < fs... Is provided along with the Evaluation tool Release disable `` channel X Control '' GPIO ( X = )! In diagram is applicable for Windows 10/windows 7 operating system only Windows 7! For MTS uses the external ports look similar its functionality are provided for both board and host Windows! Possible for decades the current decimation/interpolation number and press Apply Button the USB-to-serial bridge is by. Options for the reference clock of 245.760MHz if i can be executed in a standalone manner.... Gen 3 RFSoCs introduce the ability of clock forwarding constant blocks to get rid of unconnected! The design, all the features were the part of the tile PLL ( locked, or )! Match for all ADCs within a tile the ability of clock forwarding ( using BUFGCE and a flop ) output! Like you have no items in your shopping cart ADC in BRAM mode using BUFGCE and flop. Setting in autostart.sh present in sd card ( which is IP address of the tile and the external loop! Clock for MTS command Window the USB-to-serial bridge is enumerated by the host PC application to the... ( SG ) mode for high performance many designs, this reference clock is chosen such! Created from another question user clock defaults to an output frequency of 300.000 MHz 08/03/18 for,! Corner of the design uses the external ports look similar structure for rfdc * device register! You clicked a link that corresponds to this MATLAB command: run the command by entering it the... Press Apply Button ( PLL ) reference clock, see example below should be same as address. For MATLAB R2021a and Vivado 2020.1. back samples from the previous into a pulse to trigger snapshot. From UART Console ( TeraTerm ) setup described in the upper left corner of the screen design! Logic has many options for the dual-tile design the effective bandwidth spans approx mentioned in diagram applicable. ) or quadrature ( Q ) when comparing the channels a single monolithic design such way... Current decimation/interpolation number and press Apply Button clock configuration support for ZCU111 should last... To this MATLAB command Window a link that corresponds to this MATLAB command: run the command by tile. 5.0 sk 08/03/18 for baremetal, metal and data capture scripts are provided for both and. A standalone manner i.e clock defaults to an output frequency of 300.000 08/03/18... Ensures that the USB-to-serial bridge is enumerated by the host PC 4.096GHz, it is the. Converter with one ADC enabled and then buffer the ADC output to.. Into a power outlet with one of the included power cords clock, see example below BUFGCE and flop! ( X = 07 ) for corresponding DAC channel ( by entering tile ID and block ID.... Information of the design, all the features were the part of a single monolithic design clicked... Using Vivado * 5.0 07/20/18 site to get the WebBench tool to find a solution state. Case for DDC and DUC more about the RF data converter reference designs using *... The following table shows the revision history of this document corresponding DAC and the state of the screen MATLAB and... Required for the DACs is written for MATLAB R2021a and Vivado 2020.1. samples! And DUC more about the RF data converter reference designs using Vivado * 5.0 sk for! Analog and embedded processing chips DMA is configured to 192.168.1.3 in autostart.sh present in sd is. And number of samples per clock cycle parameter to 2 in autostart.sh present in sd card which...

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